Low power consumption in a Soc (System on Chip) is increasingly important. The designs of Socs incorporate many techniques to reduce power consumption. One technique is for the designer to use multiple voltage levels, since the voltage needs to be high only for high frequency modules of the SoC, and low voltage levels reduce power consumption. Modules of a Soc that have voltages powering them that are different from the voltages powering some other module to which they are connected are called Voltage Domains. Another technique to reduce power consumption is to turn power off completely from a module during the time that it does not need to be powered. Voltage domains one or more of whose supply voltages is dynamically turned ON/OFF are called Power Domains. Turning power OFF completely is becoming more effective compared to clock disabling as circuit design rules shrink and the leakage current increases compared to the switching current. These modern techniques along with others create new requirements in the Soc design. Some of these requirements are:                A level shifter is needed between the output port of a module that is connected to the input port of another module whenever the two ports (that is, the logic connected to the two ports) are powered with a different voltage.        A register-state retention and restore circuit may be needed for critical registers of a module when the power to a module is removed.        Isolation circuits are needed following an output port of a module whose power is turned off (port floats) and the port is connected to an input port of a module that is powered.        Logic circuits for dynamically turning power on/off on some or all of the power ports of some or all the modules need to be added.        
A power verification tool needs to determine when such additional circuits are required and when they are not required. Power State Tables (PSTs) have key information that helps decipher this requirement. A global power state table contains different power supplies used in a SoC as columns, and all possible combinations of ON/OFF and other possible states (voltage values) that may occur during SoC operation as rows. Given a connection between an output port and an input port, and knowing which power supplies power these 2 ports, the power state table shows for example which of the ON/OFF combinations for the 2 power supplies can ⋅occur, whether there are different voltage levels between the supplies, and therefore what additional circuitry if any is needed between the input and output ports.
SoC developers normally specify the power architecture (definition of voltage/power domains, use of retention registers and more) in separate files from the logic design specification. The power architecture specification is usually called the “power intent” (PI) and is, expressed in languages like Unified Power Format (UPF); described in the IEEE Standard for Design and Verification of Low-Power Integrated Circuits. This IEEE standard establishes a format used to define the power intent for electronic systems and electronic intellectual property (IP) The format provides the ability to specify the power supply network, switches, isolation, retention, and other aspects relevant to power management of an electronic system. The standard defines the relationship between the power intent specification and the logic design specification captured via other formats [e.g., standard hardware description languages (HDLs)].
Electronic design automation (EDA) tools like Spyglass from the assignee verify the power architecture of an electronic design by comparing the power intent specification to the logic design and checking for coherence, correctness and the existence of necessary power-interface components.
Traditional power verification systems create one large power state table containing all the power supplies of the SoC. As Socs increase in size and complexity, the number of power supplies and voltage domains increase and can become several scores in number, all so that power consumption can be kept down. But this causes an explosion in the size of the power state table (PST), the time needed to create it, and the resources needed to store it.
As Soc designs continue to grow in terms of complexity and number of transistors, the verification times increase and the memory requirements of the EDA tools grow. Power verification is one of the last development activities before tape-out, so SoC developers are under pressure to complete it quickly. Soc developers would benefit greatly if the verification time could be reduced from days to hours.